Relative sea-level change in Newfoundland, Canada during the past ∼3000 years

Several processes contributing to coastal relative sea-level (RSL) change in the North Atlantic Ocean are observed and/or predicted to have distinctive spatial expressions that vary by latitude. To expand the latitudinal range of RSL records spanning the past ∼3000 years and the likelihood of recognizing the characteristic fingerprints of these processes, we reconstructed RSL at two sites (Big River and Placentia) in Newfoundland from salt-marsh sediment. Bayesian transfer functions established the height of former sea level from preserved assemblages of foraminifera and testate amoebae. Age-depth models constrained by radiocarbon dates and chronohorizons estimated the timing of sediment deposition. During the past ∼3000 years, RSL rose by ∼3.0 m at Big River and by ∼1.5 m at Placentia. A locally calibrated geotechnical model showed that post-depositional lowering through sediment compaction was minimal. To isolate and quantify contributions to RSL from global, regional linear, regional non-linear, and local-scale processes, we decomposed the new reconstructions (and those in an expanded, global database) using a spatio-temporal statistical model. The global component confirms that 20th century sea-level rise occurred at the fastest, century-scale rate in over 3000 years (P > 0.999). Distinguishing the contributions from local and regional non-linear processes is made challenging by a sparse network of reconstructions. However, only a small contribution from local-scale processes is necessary to reconcile RSL reconstructions and modeled RSL trends. We identified three latitudinally-organized groups of sites that share coherent regional non-linear trends and indicate that dynamic redistribution of ocean mass by currents and/or winds was likely an important driver of sea-level change in the North Atlantic Ocean during the past ∼3000 years

High-speed and high-resolution analog-to-digital and digital-to-analog converters

Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog filtering of input signals before they are applied to an A/D converter are defined. In the case of a D/A converter the amount of filtering of the repetitive signal bands around multiples of the sampling frequency is given. This filtering is needed to avoid overloading of, for example, a power output amplifier. In chapter three the converter specifications are discussed. DC specifications are well known and can be measured with high accuracy. When these converters are applied in digital audio and digital video systems, dynamic specifications are needed. The signal-to-noise plus distortion and the Effective Resolution Bandwidth prove to be good characterization parameters. In chapter four measurement set-ups and measurement methods are introduced to verify the performance definitions given in the previous chapter. La chapter five high-speed A/D converters using a folding and interpolation scheme are described. The folding scheme is a good compromise between power consumption and circuit complexity, which results in a small die size. Timing errors introduced by long wires are easier to handle in these folding systems. In chapter 6 a theoretical treatment of the signal-dependent delay of zero crossings of limiting amplifiers is given. In nearly every converter such a nonlinear amplifier is used to amplify or compare signals. This non-linear delay results in third-order signal distortion at high frequencies. This distortion limits the Effective Resolution Bandwidth of converters. The maximum analog input frequency range is obtained when the third-order distortion component equals half a least significant bit value. In chapter seven high-resolution A/D and D/A converters are discussed. In these converters a special technique called Dynamic Element Matching is used to obtain the high bit-weighting accuracy. This technique combines an accurate passive current division with an interchanging method using time division. As a result, the final accuracy is equal to the product of two small errors. The final accuracy of this system is more than adequate for applications in 16- and 18- bit systems. Sample-and-hold amplifiers are described in chapter eight. A sample-and-hold unit is a key element in successive-approximation analog-to-digital conversion. Samples are taken at well-defined time moments and the information is kept stable during the time in which the conversion takes place. In the field of high-accuracy sample-and- hold amplifiers there are not too many devices available on the market with performances adequate for digital audio. Finally, in chapter nine reference current sources based on the bandgap principle of silicon are discussed. Although bandgap voltage reference circuits are well know, implementations to obtain reference currents with a minimum number of resistors are less well known. A second solution is given which perforns a second-order temperature compensation, resulting in a reduction of the temperature coefficient by one order of magnitude. At the same time the proportional to absolute temperature voltage difference is increased by a factor two. This results in an improvement of the signal-to-noise ratio. Chapter ten contains the final conclusions.Electrical Engineering, Mathematics and Computer Scienc

An 80 MHz, 80 mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing

An analog-to-digital converter incorporating a distributed track-and-hold preprocessing combined with folding and interpolation techniques has been designed in CMOS technology. The presented extension of the well known folding concept has resulted in a 75 MHz maximum full-scale input signal frequency. A signal-to-noise ratio of 44 dB is obtained for this frequency. The 8-b A/D converter achieves a clock frequency of 80 MHz with a power dissipation of 80 mW from a 3.3 V supply voltage. The active chip area is 0.3 mm2 in 0.5-µm standard digital CMOS technolog